Micron Promises to Break Through Memory Wall with New Technology

[phyzik]

http://pc.gamespy.com/articles/119/1190727p1.html

Company claims technology capable of 20-times the performance of DDR3.

Memory and semiconductor maker Micron believes it has broken through the DRAM memory wall, creating an entirely new category it refers to as Hybrid Memory Cube technology. And if the company's vision becomes a reality, your next-gen rig won't be sporting DDR3 SDRAM, it will have HMC.

http://pcmedia.gamespy.com/pc/image/article/119/1190727/hmc_1314305119.jpg

Tom's Hardware reports that Micron showed off the HMC prototype at the recent Hot Chips 23 conference, unveiling a technology it claims is capable of 20-times the performance of a current DDR3 module, while using one-tenth as much energy per bit. See Micron describe the tech below:

kaV2nZSkw8A

Micron notes that Hybrid Memory Cube technology is a work in progress, and the company is not yet ready to speculate on when it will go to market or in what form.

[vander]

Go Micron!

[Wild Cobra]

Looks good.

If anyone knew when and if this would be a reality, it would be good to buy stock just before.

But that would be inside trading.

[Wild Cobra]

From Micron's site:

Innovations: Hybrid Memory Cube (http://www.micron.com/innovations/hmc.html)

[ElNono]

If it's a public release, how is it inside trading? :lol smh

[Wild Cobra]

If it's a public release, how is it inside trading? :lol smh
The public release didn't indicate this idea would pan out for certain. Timing of when and if it does would be the key.

Do you realize how complex the process becomes to do this? It's possible they will never achieve it with any usable reliability.

[Trainwreck2100]

Thats alot of porn

[ElNono]

The public release didn't indicate this idea would pan out for certain. Timing of when and if it does would be the key.

Micron has functioning prototypes on silicon today.

Micron is currently working with high-performance computing and networking companies but, like most high-performance technologies, this is expected to work its way to the consumer space in some form. "We would see this working its way to commercial (corporate) solutions as early as 2012, with significant volumes in 2013. These kind of technologies will start to work their way toward the consumer space in 2015, 2016," he said.


There's your insider trading :rolleyes


Do you realize how complex the process becomes to do this? It's possible they will never achieve it with any usable reliability.

The TSV technology used dates back to 2004 by Intel. Looks like you don't know much about it. The biggest hurdle is transforming fabs to build these 3D ICs instead of the current single-layer crop.

[Wild Cobra]

Micron has functioning prototypes on silicon today.

Micron is currently working with high-performance computing and networking companies but, like most high-performance technologies, this is expected to work its way to the consumer space in some form. "We would see this working its way to commercial (corporate) solutions as early as 2012, with significant volumes in 2013. These kind of technologies will start to work their way toward the consumer space in 2015, 2016," he said.


There's your insider trading :rolleyes



The TSV technology used dates back to 2004 by Intel. Looks like you don't know much about it. The biggest hurdle is transforming fabs to build these 3D ICs instead of the current single-layer crop.
A prototype is a far cry different than doing 3d gates and using the small architecture together.

If you've ever read tech materiel for future development, then followed the timeline, it doesn't always pan out. I was in the forefront of 300mm design in 1995-1996. Look how long until it was finally used. We made a prototype machine and did 300mm process in late 1996. It was still some time. I also worked with a copper process in 1994 with Intel PTD.

I'll believe the process when I see it in production.

[ElNono]

A prototype is a far cry different than doing 3d gates and using the small architecture together.

Not sure what part of 'Micron has functioning prototypes on silicon today' you didn't understand. That's a working copy.
TMSC already has fabs able to produce 3D chips (rumored Apple A6 being a quad-core 3D design)


If you've ever read tech materiel for future development, then followed the timeline, it doesn't always pan out. I was in the forefront of 300mm design in 1995-1996. Look how long until it was finally used. We made a prototype machine and did 300mm process in late 1996. It was still some time. I also worked with a copper process in 1994 with Intel PTD.

:lol nobody cares what you did in ancient ages
:lol motorola 68k
:lol 7 year old technology is 'new'

[Wild Cobra]

Not sure what part of 'Micron has functioning prototypes on silicon today' you didn't understand. That's a working copy.
TMSC already has fabs able to produce 3D chips (rumored Apple A6 being a quad-core 3D design)



:lol nobody cares what you did in ancient ages
:lol motorola 68k
:lol 7 year old technology is 'new'
There are still problems encountered.

Yes, I'm out of the loop. I can barely imaging the new 20nm processes in place. To take these extremes of lithography, CMP, deposition, etc. to those levels, and then, build more gates above at least 4 layers of metal...

Maybe it's just too much for me to imagine.

Yes, 3D has been dome for years, as in layers of conductors. 7 layers of metal was the commonplace for some processes. Are there any chips sold that have gates above gates? That would be transisters on the substrate, then a few layers of metal, then a SOG process or something else for more gates, then more metal layers, then more gates, etc...

Just how many processes and layers total does this become? At these sizes the failure rate is pretty high to begin with. This failure rate increases with each layer. At some point, you end up with a very low yield which makes the product rather expensive.

Now assume you end up with numbers that pan out for profitability. What is their failure rate over a year or two?

[ElNono]

There hasn't been a need for 3D chips because they could still keep on reducing the nm spacing and reducing voltage to avoid parasitic capacitance. But obviously, as limits get harder to overcome, parallel research in other design methods (like TSV) have gone on fairly strongly. There's actually 4 different ways to do TSV these days.

But if you want to look for a functional 3D chip CPU, google up "Rochester Cube".

[Wild Cobra]

It still looks like they are a ways away from going prototype to production.

[ElNono]

smh

[MannyIsGod]

smh

:lol

[vy65]

For some reason, I thought WC was a retired mailman.

[DMC]

Generic brochure style video. Doesn't do much in the way of explaining the process. There are some roadblocks in production for this kind of thing. I would like to see how many of these they can get per 12" wafer and what the production costs would be.

[DMC]

There hasn't been a need for 3D chips because they could still keep on reducing the nm spacing and reducing voltage to avoid parasitic capacitance. But obviously, as limits get harder to overcome, parallel research in other design methods (like TSV) have gone on fairly strongly. There's actually 4 different ways to do TSV these days.

But if you want to look for a functional 3D chip CPU, google up "Rochester Cube".

ASML made big strides in reducing photolithographic line width using immersion technology (some time ago).

I haven't heard that Micron is building a new fab, which they may be required to do if existing fabs cannot support that technology. I wonder who's doing the pilot line on that one. Then again it could be just a build thing that doesn't require more than a common 12" fab can do.

[ElNono]

ASML made big strides in reducing photolithographic line width using immersion technology (some time ago).

I haven't heard that Micron is building a new fab, which they may be required to do if existing fabs cannot support that technology. I wonder who's doing the pilot line on that one. Then again it could be just a build thing that doesn't require more than a common 12" fab can do.

TSMC is supposed to have a fab working already, and it's racing to beat Intel who announced their 22nm Ivy Bridge chips (which also use a similar 3D concept) to the end of this year. Looks like Intel actually might hold on releasing Ivy Bridge until early next year.

TSMC being the company that is now making ARM cpu's for Apple (replacing Samsung) and the new A6 processor is rumored to be a 4-core 3D chip also.

There's different ways to achieve the 3D concept. For example, not all 3D chips will gain on bandwidth, but will instead gain on reduced power usage. The tri-gate 3D (http://en.wikipedia.org/wiki/Multigate_device#Tri-gate_transistors_.28Intel.29) tech Intel is using in Ivy Bridge is pretty cool if you haven't read about it yet.

Micron actually has 3 fabs (Singapore; Lehi, Utah; Manassas, Virginia) all shared with Intel.

[Wild Cobra]

For some reason, I thought WC was a retired mailman.
No, but I did a temporary gig, as a mail carrier between jobs.

[Wild Cobra]

Generic brochure style video. Doesn't do much in the way of explaining the process. There are some roadblocks in production for this kind of thing. I would like to see how many of these they can get per 12" wafer and what the production costs would be.
There's no such thing as a 12" wafer. It's 300mm.

[ElNono]

There's no such thing as a 12" wafer. It's 300mm.

Which is usually referred to as 12 inch (even though it's 11.8)

[Wild Cobra]

ASML made big strides in reducing photolithographic line width using immersion technology (some time ago).

I haven't heard that Micron is building a new fab, which they may be required to do if existing fabs cannot support that technology. I wonder who's doing the pilot line on that one. Then again it could be just a build thing that doesn't require more than a common 12" fab can do.
Prototyping would probably be done with 150mm or 200mm equipment. When 200mm was dominant, I worked with an Intel skunkworks guy on 150mm equipment, prototyping a copper process. The CMP equipment was actually a 200mm platform, but with a 150mm head.

[Wild Cobra]

Which is usually referred to as 12 inch (even though it's 11.8)
Not by professionals. Sure, they use it to talk to the non-tech shareholders, but that's about it. Inside, it's 300mm.

[ElNono]

Not by professionals. Sure, they use it to talk to the non-tech shareholders, but that's about it. Inside, it's 300mm.

Not really. It's referred to as 12 inch industry-wide.

Obviously, you're not part of the industry, that's probably why you don't know what you're talking about. Nothing new there.

[Wild Cobra]

Not really. It's referred to as 12 inch industry-wide.

Obviously, you're not part of the industry, that's probably why you don't know what you're talking about. Nothing new there.
Then the industry is dumbing down since I was in the loop.

[ElNono]

Then the industry is dumbing down since I was in the loop.

I would argue that the industry lost dead weight.

[Wild Cobra]

I would argue that the industry lost dead weight.
You must be one of those metric deniers.

[ElNono]

You must be one of those metric deniers.

I come from a metric country. So, no. I just have a good idea when somebody is talking out of their ass.

[TinTin]

:lol

[Wild Cobra]

I come from a metric country. So, no. I just have a good idea when somebody is talking out of their ass.

I know your origins, but figured you must want to get rid of all traces.

[DMC]

There's no such thing as a 12" wafer. It's 300mm.



1-inch (25 mm)
2-inch (51 mm). Thickness 275 µm (http://en.wikipedia.org/wiki/%CE%9Cm).
3-inch (76 mm). Thickness 375 µm.
4-inch (100 mm). Thickness 525 µm.
5-inch (130 mm) or 125 mm (4.9 inch). Thickness 625 µm.
150 mm (5.9 inch, usually referred to as "6 inch"). Thickness 675 µm.
200 mm (7.9 inch, usually referred to as "8 inch"). Thickness 725 µm.
300 mm (11.8 inch, usually referred to as "12 inch"). Thickness 775 µm.
450 mm ("18 inch"). Thickness 925 µm (expected).[12] (http://en.wikipedia.org/wiki/Wafer_%28electronics%29#cite_note-11)


Industry talk. Not Google talk.

[DMC]

A prototype is a far cry different than doing 3d gates and using the small architecture together.

If you've ever read tech materiel for future development, then followed the timeline, it doesn't always pan out. I was in the forefront of 300mm design in 1995-1996. Look how long until it was finally used. We made a prototype machine and did 300mm process in late 1996. It was still some time. I also worked with a copper process in 1994 with Intel PTD.

I'll believe the process when I see it in production.

What machine?

[DMC]

Prototyping would probably be done with 150mm or 200mm equipment. When 200mm was dominant, I worked with an Intel skunkworks guy on 150mm equipment, prototyping a copper process. The CMP equipment was actually a 200mm platform, but with a 150mm head.

I highly doubt a fab would retool to prototype. A pilot line would be introduced in the line and would be walked through, unless a group like SVTC (formerly Sematech) took the contract, but then 150mm equipment doesn't have the ability to do narrow line widths or meet the .15u particle requirements, and most are not in class 1 cleanrooms.

Also, going from 150mm to 300mm isn't as easy as just changing recipes and tool sets. Some things don't transfer well. Too many costs involved in a pilot line that won't be anything like the production line.

[Wild Cobra]

I highly doubt a fab would retool to prototype. A pilot line would be introduced in the line and would be walked through, unless a group like SVTC (formerly Sematech) took the contract, but then 150mm equipment doesn't have the ability to do narrow line widths or meet the .15u particle requirements, and most are not in class 1 cleanrooms.

Also, going from 150mm to 300mm isn't as easy as just changing recipes and tool sets. Some things don't transfer well. Too many costs involved in a pilot line that won't be anything like the production line.
Sorry, but I know what happened in the past and I wasn't talking about a pilot line, but what happens before that. It isn't unlikely that some companies prototyping is done on 200mm. Most larger tools can be scaled down for smaller wafer sizes. Some older equipment is also partially modernized, saving R&D cost. I'm talking prototype equipment and process engineering. Not pilot lines. That comes later.

I have worked with SemaTech when I worked on prototype 300mm process equipment in 1996 as an Engineering Technician. Just looked them up. They are still SemaTech. They are not a single entity, but a consortium. Do you know what are you talking about?

SEMATECH News (http://www.sematech.org/corporate/news/releases/20071204.htm)

[ElNono]

Size and process of the wafer don't really matter. AFAIK, most companies are using die-on-die manufacturing. Meaning each wafer is manufactured normally as a 2D IC, then diced, thinned, aligned, bonded and TSV connected. The actual assembling of the 3D layers is done as a post-process of die creation and before encapsulation. That allows the companies to keep using the current fabs normally, and just add an extra stage. A variation of this method is die-on-wafer, where the lower layer wafer is not diced while the upper layers are, and then the upper dies are bonded to the lower wafer, although I have not heard companies using this manufacturing method.

Other methods, like monolithic 3D manufacturing would require a new type of fab, and a method like wafer-on-wafer would result in lower yields.

[DMC]

Sorry, but I know what happened in the past and I wasn't talking about a pilot line, but what happens before that. It isn't unlikely that some companies prototyping is done on 200mm. Most larger tools can be scaled down for smaller wafer sizes. Some older equipment is also partially modernized, saving R&D cost. I'm talking prototype equipment and process engineering. Not pilot lines. That comes later.

I have worked with SemaTech when I worked on prototype 300mm process equipment in 1996 as an Engineering Technician. Just looked them up. They are still SemaTech. They are not a single entity, but a consortium. Do you know what are you talking about?

SEMATECH News (http://www.sematech.org/corporate/news/releases/20071204.htm)

I know what I am talking about.

I specifically said "pilot line".

I know about Sematech. I didn't say Sematech closed. I said SVTC was formerly Sematech. SVTC occupies the fab that Sematech once occupied in Austin. I am well aware that Sematech still exists.

Tell me about your machine.

[Wild Cobra]

I know what I am talking about.

I specifically said "pilot line".

I know about Sematech. I didn't say Sematech closed. I said SVTC was formerly Sematech. SVTC occupies the fab that Sematech once occupied in Austin. I am well aware that Sematech still exists.

Tell me about your machine.
This is what came from the 300mm prototype:

SpeedFam-IPEC Unveils 300mm Momentum (http://www.edn.com/article/485117-SpeedFam_IPEC_Unveils_300mm_Momentum.php)

IPEC didn't know how to keep the technology working they bought though. Those of us who knew it stayed in Portland.

IPEC to acquire Gaard Automation (http://findarticles.com/p/articles/mi_m0EKF/is_n2083_v41/ai_17605425/)

It was the best job I ever had, saw the writing on the wall after IPEC purchased it. Left for a different job, and glad I did. About a year after I left, IPEC moved development and manufacturing to Phoenix.

This is what we were making when I left:

IPEC 776 AUTOMATED CMP TOOL (http://www.axustech.com/IPEC776.HTML)

http://www.axustech.com/images/776.jpg

[DMC]

Cool.

[Wild Cobra]

h2swEqw6pbg

[Wild Cobra]

Hybrid Memory Cube Moves Forward (http://hybridmemorycube.org/files/SiteDownloads/20120710_MediaEntertainmentTech_HMCMovesForward.pd f)

[TDMVPDPOY]

fck these clowns are expensive....i stick to 3rd party competitors

[Wild Cobra]

fck these clowns are expensive....i stick to 3rd party competitors
That's not a simple process these cubes are undergoing. I'll bet they have several missions of dollars of research they have to recoup also.

3rd party competition...

Maybe, but unlikely. They would have to steal patented ideas.