Reply With Quote
Go Micron!
http://pc.gamespy.com/articles/119/1190727p1.html
Company claims technology capable of 20-times the performance of DDR3.
Memory and semiconductor maker Micron believes it has broken through the DRAM memory wall, creating an entirely new category it refers to as Hybrid Memory Cube technology. And if the company's vision becomes a reality, your next-gen rig won't be sporting DDR3 SDRAM, it will have HMC.
Tom's Hardware reports that Micron showed off the HMC prototype at the recent Hot Chips 23 conference, unveiling a technology it claims is capable of 20-times the performance of a current DDR3 module, while using one-tenth as much energy per bit. See Micron describe the tech below:
Micron notes that Hybrid Memory Cube technology is a work in progress, and the company is not yet ready to speculate on when it will go to market or in what form.
Go Micron!
Looks good.
If anyone knew when and if this would be a reality, it would be good to buy stock just before.
But that would be inside trading.
From Micron's site:
Innovations: Hybrid Memory Cube
If it's a public release, how is it inside trading?smh
The public release didn't indicate this idea would pan out for certain. Timing of when and if it does would be the key.If it's a public release, how is it inside trading?
Do you realize how complex the process becomes to do this? It's possible they will never achieve it with any usable reliability.
Thats alot of porn
Micron has functioning prototypes on silicon today.
Micron is currently working with high-performance computing and networking companies but, like most high-performance technologies, this is expected to work its way to the consumer space in some form. "We would see this working its way to commercial (corporate) solutions as early as 2012, with significant volumes in 2013. These kind of technologies will start to work their way toward the consumer space in 2015, 2016," he said.
There's your insider trading
The TSV technology used dates back to 2004 by Intel. Looks like you don't know much about it. The biggest hurdle is transforming fabs to build these 3D ICs instead of the current single-layer crop.
A prototype is a far cry different than doing 3d gates and using the small architecture together.Micron has functioning prototypes on silicon today.
Micron is currently working with high-performance computing and networking companies but, like most high-performance technologies, this is expected to work its way to the consumer space in some form. "We would see this working its way to commercial (corporate) solutions as early as 2012, with significant volumes in 2013. These kind of technologies will start to work their way toward the consumer space in 2015, 2016," he said.
There's your insider trading
The TSV technology used dates back to 2004 by Intel. Looks like you don't know much about it. The biggest hurdle is transforming fabs to build these 3D ICs instead of the current single-layer crop.
If you've ever read tech materiel for future development, then followed the timeline, it doesn't always pan out. I was in the forefront of 300mm design in 1995-1996. Look how long until it was finally used. We made a prototype machine and did 300mm process in late 1996. It was still some time. I also worked with a copper process in 1994 with Intel PTD.
I'll believe the process when I see it in production.
Not sure what part of 'Micron has functioning prototypes on silicon today' you didn't understand. That's a working copy.
TMSC already has fabs able to produce 3D chips (rumored Apple A6 being a quad-core 3D design)
There are still problems encountered.Not sure what part of 'Micron has functioning prototypes on silicon today' you didn't understand. That's a working copy.
TMSC already has fabs able to produce 3D chips (rumored Apple A6 being a quad-core 3D design)
Yes, I'm out of the loop. I can barely imaging the new 20nm processes in place. To take these extremes of lithography, CMP, deposition, etc. to those levels, and then, build more gates above at least 4 layers of metal...
Maybe it's just too much for me to imagine.
Yes, 3D has been dome for years, as in layers of conductors. 7 layers of metal was the commonplace for some processes. Are there any chips sold that have gates above gates? That would be transisters on the substrate, then a few layers of metal, then a SOG process or something else for more gates, then more metal layers, then more gates, etc...
Just how many processes and layers total does this become? At these sizes the failure rate is pretty high to begin with. This failure rate increases with each layer. At some point, you end up with a very low yield which makes the product rather expensive.
Now assume you end up with numbers that pan out for profitability. What is their failure rate over a year or two?
There hasn't been a need for 3D chips because they could still keep on reducing the nm spacing and reducing voltage to avoid parasitic capacitance. But obviously, as limits get harder to overcome, parallel research in other design methods (like TSV) have gone on fairly strongly. There's actually 4 different ways to do TSV these days.
But if you want to look for a functional 3D chip CPU, google up "Rochester Cube".
It still looks like they are a ways away from going prototype to production.
smh
For some reason, I thought WC was a retired mailman.
Generic brochure style video. Doesn't do much in the way of explaining the process. There are some roadblocks in production for this kind of thing. I would like to see how many of these they can get per 12" wafer and what the production costs would be.
ASML made big strides in reducing photolithographic line width using immersion technology (some time ago).
I haven't heard that Micron is building a new fab, which they may be required to do if existing fabs cannot support that technology. I wonder who's doing the pilot line on that one. Then again it could be just a build thing that doesn't require more than a common 12" fab can do.
TSMC is supposed to have a fab working already, and it's racing to beat Intel who announced their 22nm Ivy Bridge chips (which also use a similar 3D concept) to the end of this year. Looks like Intel actually might hold on releasing Ivy Bridge until early next year.
TSMC being the company that is now making ARM cpu's for Apple (replacing Samsung) and the new A6 processor is rumored to be a 4-core 3D chip also.
There's different ways to achieve the 3D concept. For example, not all 3D chips will gain on bandwidth, but will instead gain on reduced power usage. The tri-gate 3D tech Intel is using in Ivy Bridge is pretty cool if you haven't read about it yet.
Micron actually has 3 fabs (Singapore; Lehi, Utah; Manassas, Virginia) all shared with Intel.
No, but I did a temporary gig, as a mail carrier between jobs.
There's no such thing as a 12" wafer. It's 300mm.
Which is usually referred to as 12 inch (even though it's 11.8)
Prototyping would probably be done with 150mm or 200mm equipment. When 200mm was dominant, I worked with an Intel skunkworks guy on 150mm equipment, prototyping a copper process. The CMP equipment was actually a 200mm platform, but with a 150mm head.
Not by professionals. Sure, they use it to talk to the non-tech shareholders, but that's about it. Inside, it's 300mm.
Not really. It's referred to as 12 inch industry-wide.
Obviously, you're not part of the industry, that's probably why you don't know what you're talking about. Nothing new there.
There are currently 1 users browsing this thread. (0 members and 1 guests)
Posting Permissions
